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<< 点击显示目录 >> 主页 振动监测 > X20(c)CM4810使用手册 > 寄存器说明 - Register description > Flat 流 - Flatstream > Flat流通信 - Flatstream communication > Flat流模式的寄存器 - Registers for Flatstream mode > Flat流操作 - Flatstream operation > 模块的通信状态 - Communication status of the module |
Name:
InputSequence
名称:
InputSequence
Register "InputSequence" contains information about the communication status of the module. It is written by the module and should only be read by the CPU.
寄存器 "InputSequence" 中包含关于模块的通信状态的信息。它由模块写入，只能由CPU读取。
Data type 数据类型 |
Values 值 |
|---|---|
USINT |
See the bit structure. 请参阅位结构。 |
Bit 位 |
Description 描述 |
Value 值 |
Information 说明 |
|---|---|---|---|
0 - 2 |
InputSequenceCounter 输入序列计数器 |
0 - 7 |
Counter for sequences issued in the input direction 在输入方向发出的序列的计数器 |
3 |
InputSyncBit 输入同步位 |
0 |
Not ready (disabled) 未就绪 (禁用) |
1 |
就绪 (使能) |
||
4 - 6 |
OutputSequenceAck 输出序列确认 |
0 - 7 |
Mirrors OutputSequenceCounter 输出序列计数器的镜像 |
7 |
OutputSyncAck 输出同步确认 |
0 |
Not ready (disabled) 未就绪 (禁用) |
1 |
Ready (enabled) 就绪 (使能) |
The InputSequenceCounter is a continuous counter of sequences that have been issued by the module. The module uses InputSequenceCounter to direct the CPU to accept a sequence (the input direction must be synchronized when this happens).
InputSequenceCounter 是一个由模块发出的序列的连续计数器。模块使用 InputSequenceCounter 来指示 CPU 接收序列（发生这种情况时，输入方向必须是同步的）。
The module uses InputSyncBit to attempt to synchronize the input channel.
模块使用 InputSyncBit 来尝试同步输入通道。
OutputSequenceAck is used for acknowledgment. The value of OutputSequenceCounter is mirrored if the module has received a sequence successfully.
OutputSequenceAck 用于确认。如果模块已成功接收序列，则会镜像输出序列计数器的值。
The OutputSyncAck bit acknowledges the synchronization of the output channel for the CPU. This indicates that the module is ready to receive data.
OutputSyncAck 位确认了 CPU 输出通道的同步。这表示模块已准备好接收数据。