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<< 点击显示目录 >> 主页 振动监测 > X20(c)CM4810使用手册 > 寄存器说明 - Register description > Flat 流 - Flatstream > Flat流通信 - Flatstream communication > Flat流模式的寄存器 - Registers for Flatstream mode > Flat流操作 - Flatstream operation > CPU 的通信状态 - Communication status of the CPU |
Name:
OutputSequence
名称:
OutputSequence
Register "OutputSequence" contains information about the communication status of the CPU. It is written by the CPU and read by the module.
寄存器 “OutputSequence” 中包含有关CPU通信状态的信息。它由CPU写入并由模块读取。
Data type 数据类型 |
Values 值 |
|---|---|
USINT |
See the bit structure. 请参阅位结构。 |
Bit 位 |
Description 描述 |
Value 值 |
Information 说明 |
|---|---|---|---|
0 - 2 |
OutputSequenceCounter 输出序列计数器 |
0 - 7 |
Counter for the sequences issued in the output direction 在输出方向发出的序列的计数器 |
3 |
OutputSyncBit 输出同步位 |
0 |
Output direction disabled 输出方向禁用 |
1 |
Output direction enabled 输出方向启用 |
||
4 - 6 |
InputSequenceAck 输入序列确认 |
0 - 7 |
Mirrors InputSequenceCounter 输入序列计数器的镜像 |
7 |
InputSyncAck 输入同步确认 |
0 |
Input direction not ready (disabled) 输入方向未就绪 (禁用) |
1 |
Input direction ready (enabled) 输入方向已就绪 (使能) |
The OutputSequenceCounter is a continuous counter of sequences that have been issued by the CPU. The CPU uses OutputSequenceCounter to direct the module to accept a sequence (the output direction must be synchronized when this happens).
OutputSequenceCounter 是一个由CPU发出的序列的连续计数器。模块使用 OutputSequenceCounter 来指示模块接收序列（发生这种情况时，输出方向必须是同步的）。
The CPU uses OutputSyncBit to attempt to synchronize the output channel.
CPU使用 OutputSyncBit 来尝试同步输出通道。
InputSequenceAck is used for acknowledgment. The value of InputSequenceCounter is mirrored if the CPU has received a sequence successfully.
InputSequenceAck 用于确认。如果CPU已成功接收序列，则会镜像输入序列计数器的值。
The InputSyncAck bit acknowledges the synchronization of the input channel for the module. This indicates that the CPU is ready to receive data.
InputSyncAck 位确认了模块输入通道的同步。这表示CPU已准备好接收数据。