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X20CM4800X - Data sheet V1.04
InputSequence
Register "InputSequence" contains information about the communication status of the module. It is written by the module and should only be read by the CPU.
Bit structure:
Description |
Value |
Information |
|
0 - 2 |
InputSequenceCounter |
0 - 7 |
Counter for sequences issued in the input direction |
3 |
InputSyncBit |
0 |
Not ready (disabled) |
1 |
Ready (enabled) |
||
4 - 6 |
OutputSequenceAck |
0 - 7 |
Mirrors OutputSequenceCounter |
7 |
OutputSyncAck |
0 |
Not ready (disabled) |
1 |
Ready (enabled) |
InputSequenceCounter
The InputSequenceCounter is a continuous counter of sequences that have been issued by the module. The module uses InputSequenceCounter to direct the CPU to accept a sequence (the input direction must be synchronized when this happens).
InputSyncBit
The module uses InputSyncBit to attempt to synchronize the input channel.
OutputSequenceAck
OutputSequenceAck is used for acknowledgment. The value of OutputSequenceCounter is mirrored if the module has received a sequence successfully.
OutputSyncAck
The OutputSyncAck bit acknowledges the synchronization of the output channel for the CPU. This indicates that the module is ready to receive data.