Communication status of the CPU

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Communication status of the CPU

X20CM4800X - Data sheet V1.04

Name:

OutputSequence

Register "OutputSequence" contains information about the communication status of the CPU. It is written by the CPU and read by the module.

Data type

Values

USINT

See the bit structure.

Bit structure:

Bit

Description

Value

Information

0 - 2

OutputSequenceCounter

0 - 7

Counter for the sequences issued in the output direction

3

OutputSyncBit

0

Output direction disabled

1

Output direction enabled

4 - 6

InputSequenceAck

0 - 7

Mirrors InputSequenceCounter

7

InputSyncAck

0

Input direction not ready (disabled)

1

Input direction ready (enabled)

OutputSequenceCounter

The OutputSequenceCounter is a continuous counter of sequences that have been issued by the CPU. The CPU uses OutputSequenceCounter to direct the module to accept a sequence (the output direction must be synchronized when this happens).

OutputSyncBit

The CPU uses OutputSyncBit to attempt to synchronize the output channel.

InputSequenceAck

InputSequenceAck is used for acknowledgment. The value of InputSequenceCounter is mirrored if the CPU has received a sequence successfully.

InputSyncAck

The InputSyncAck bit acknowledges the synchronization of the input channel for the module. This indicates that the CPU is ready to receive data.