During synchronization, a communication channel is opened. It is important to make sure that a module is present and that the current value of SequenceCounter is stored on the station receiving the message.

Flatstream can handle full-duplex communication. This means that both channels / communication directions can be handled separately. They must be synchronized independently so that simplex communication can theoretically be carried out as well.

在同步过程中，一个通信通道被打开。重要的是要确保有一个模块存在，并且SequenceCounter的当前值存储在接收消息的站上。

Flat流可以处理全双工通信。这意味着两个信道/通信方向可以分别处理。它们必须独立同步，所以理论上也可以进行单工通信。

Synchronization in the output direction (CPU as the transmitter):

输出方向的同步（CPU作为发送端）：

The corresponding synchronization bits (OutputSyncBit and OutputSyncAck) are reset. Because of this, Flatstream cannot be used at this point in time to transfer messages from the CPU to the module.

相应的同步位（OutputSyncBit和OutputSyncAck）被重置。正因为如此，此时不能使用Flat流将消息从CPU传输到模块。

Algorithm

算法

1) The CPU must write 000 to OutputSequenceCounter and reset OutputSyncBit.

The CPU must cyclically query the high nibble of register "InputSequence" (checks for 000 in OutputSequenceAck and 0 in OutputSyncAck).

1)CPU必须向OutputSequenceCounter写入000，并重置OutputSyncBit。

CPU必须循环查询寄存器“InputSequence”的高半字节（在OutputSequenceAck中检测000，在OutputSyncAck中检测0）。

The module does not accept the current contents of InputMTU since the channel is not yet synchronized.

The module matches OutputSequenceAck and OutputSyncAck to the values of OutputSequenceCounter and OutputSyncBit.

由于通道尚未同步，模块不接受InputMTU的当前内容。

模块将OutputSequenceAck和OutputSyncAck与OutputSequenceCounter和OutputSyncBit的值进行匹配。

2) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is permitted to increment OutputSequenceCounter.

The CPU continues cyclically querying the high nibble of register "OutputSequence" (checks for 001 in OutputSequenceAck and 0 in InputSyncAck).

2) 如果CPU在OutputSequenceAck和OutputSyncAck中登记了预期的值，它被允许增加OutputSequenceCounter。

CPU继续循环查询寄存器“OutputSequence”的高半字节（在OutputSequenceAck中检测001，在InputSyncAck中检测0）。

The module does not accept the current contents of InputMTU since the channel is not yet synchronized.

The module matches OutputSequenceAck and OutputSyncAck to the values of OutputSequenceCounter and OutputSyncBit.

由于通道尚未同步，模块不接受InputMTU的当前内容。

模块将OutputSequenceAck和OutputSyncAck与OutputSequenceCounter和OutputSyncBit的值进行匹配。

3) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is permitted to increment OutputSequenceCounter.

The CPU continues cyclically querying the high nibble of register "OutputSequence" (checks for 001 in OutputSequenceAck and 1 in InputSyncAck).

3) 如果CPU在OutputSequenceAck和OutputSyncAck中登记了预期的值，它被允许增加OutputSequenceCounter。

CPU继续循环查询寄存器“OutputSequence”的高半字节（在OutputSequenceAck中检测001，在InputSyncAck中检测1）。

Note:

注意：

Theoretically, data can be transferred from this point forward. However, it is still recommended to wait until the output direction is completely synchronized before transferring data.

理论上，数据可以从这一点开始传输。但是，仍然建议等待输出方向完全同步后再传输数据。

The module sets OutputSyncAck.

该模块设置OutputSyncAck。

The output direction is synchronized, and the CPU can transmit data to the module.

输出方向已经同步，CPU可以向模块传输数据。

Synchronization in the input direction (CPU as the receiver):

输入方向的同步（CPU作为接收端）：

The corresponding synchronization bits (InputSyncBit and InputSyncAck) are reset. Because of this, Flatstream cannot be used at this point in time to transfer messages from the module to the CPU.

相应的同步位（InputSyncBit和InputSyncAck）被重置。正因为如此，此时不能使用Flat流将消息从模块传输到CPU。

Algorithm

算法

The module writes 000 to InputSequenceCounter and resets InputSyncBit.

The module monitors the high nibble of register "OutputSequence" and expects 000 in InputSequenceAck and 0 in InputSyncAck.

该模块将000写入InputSequenceCounter并重置InputSyncBit。

模块监测寄存器 "OutputSequence "的高位，期望InputSequenceAck中的000和InputSyncAck中的0。

1) The CPU is not permitted to accept the current contents of InputMTU since the channel is not yet synchronized.

The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.

1)由于通道尚未同步，因此不允许CPU接受InputMTU的当前内容。

CPU必须将InputSequenceAck和InputSyncAck与InputSequenceCounter和InputSyncBit的值相匹配。

If the module registers the expected values in InputSequenceAck and InputSyncAck, it increments InputSequenceCounter.

The module monitors the high nibble of register "OutputSequence" and expects 001 in InputSequenceAck and 0 in InputSyncAck.

如果模块在InputSequenceAck和InputSyncAck中登记了预期的值，它就会增加InputSequenceCounter。

模块监测寄存器 "OutputSequence "的高位，期望InputSequenceAck中为001，InputSyncAck为0。

2) The CPU is not permitted to accept the current contents of InputMTU since the channel is not yet synchronized.

The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.

2)由于通道尚未同步，因此不允许CPU接受InputMTU的当前内容。

CPU必须将InputSequenceAck和InputSyncAck与InputSequenceCounter和InputSyncBit的值相匹配。

If the module registers the expected values in InputSequenceAck and InputSyncAck, it sets InputSyncBit.

The module monitors the high nibble of register "OutputSequence" and expects 1 in InputSyncAck.

如果模块在InputSequenceAck和InputSyncAck中登记了预期的值，则会设置InputSyncBit。

该模块监视寄存器“OutputSequence”的高半字节，并期望InputSyncAck中有1。

3) The CPU is permitted to set InputSyncAck.

Note:

Theoretically, data could already be transferred in this cycle.

If InputSyncBit is set and InputSequenceCounter has been increased by 1, the values in the enabled Rx bytes must be accepted and acknowledged (see also "Communication in the input direction").

3)允许CPU设置InputSyncAck。

注意:

理论上，数据已经可以在这个周期内传输。

如果InputSyncBit被设置，并且InputSequenceCounter增加了1，则必须接受并确认启用的Rx字节中的值（另见 "输入方向的通信"）。

The input direction is synchronized, and the module can transmit data to the CPU.

输入方向是同步的，模块可以将数据传输到CPU。

同步 - Synchronization

同步 - Synchronization

Synchronization in the output direction (CPU as the transmitter):

输出方向的同步（CPU作为发送端）：

Algorithm

算法

Synchronization in the input direction (CPU as the receiver):

输入方向的同步（CPU作为接收端）：

Algorithm

算法